AN AREA EFFICIENT AND HIGH SPEED NOC SYSTEM BY USING OCI TECHNIQUE

Abstract

The growing complexity and performance requirements of modern System-on-Chip (SoC) designs have accelerated the shift from traditional bus-based architectures to more scalable and efficient communication solutions. Network-on-Chip (NoC) architectures have emerged as a leading paradigm, offering high scalability and the ability to meet diverse application demands. In NoCs, data is transmitted as packets between processing elements (nodes) interconnected via routers and switches. As the number of processing elements in SoCs increases, conventional bus-based systems fail to deliver the desired performance, making packet-switching NoCs a superior alternative. However, when multiple processing elements share the same physical link, collisions can occur. Code Division Multiple Access (CDMA) is a promising medium-sharing technique to prevent such collisions by allowing simultaneous communication through unique code assignments. A core component of NoCs is the crossbar, typically composed of an encoder, adder, and decoder. In conventional designs, data is transmitted as binary values (ones and zeros), which can lead to contention, particularly in CDMAbased crossbars under heavy load. This paper addresses the overloaded CDMA crossbar problem by integrating an efficient data compression technique to reduce contention and improve performance. The proposed CDMA NoC architecture optimizes code allocation and communication protocols to enhance throughput, reduce latency, and lower power consumption. The design is implemented and tested using Xilinx development tools, with simulation results demonstrating significant improvements over traditional CDMA crossbar implementations. This work serves as a foundation for future research into high-performance, scalable NoC communication infrastructures.