A LOW-POWER AND AREA-EFFICIENT DESIGN OF A WEIGHTED PSEUDORANDOM TEST-PATTERN GENERATOR FOR A TEST-PER-SCAN BUILT-IN-SELF-TEST ARCHITECTURE

Abstract

Test Pattern Generator (TPG) is an essential component in Built-In Self-Test (BIST) architectures, responsible for generating pseudorandom test patterns that can be weighted to improve fault detection efficiency while reducing the dependency on deterministic random number generators. This paper proposes a novel weighted Test Pattern Generator (TPG) along with a deterministic random number generation technique for a scan-based BIST architecture. The primary objective of the proposed design is to generate efficient weighted and deterministic test patterns that enhance fault coverage while minimizing power consumption, hardware overhead, and testing time. The proposed approach maximizes the pseudo-primary seed of the TPG to generate longer weighted and deterministic pseudorandom sequences, thereby increasing the effectiveness of the testing process. Maximum-length weighted patterns are achieved by assigning independent weights to individual scan chains through a weight-enabled clock mechanism. This selective weighting technique improves the quality of test patterns, reduces unnecessary switching activity during scan operations, and significantly lowers dynamic power consumption. Furthermore, the proposed architecture minimizes area overhead by employing an optimized hardware implementation without compromising test performance. In addition, the novel pattern generator is implemented and evaluated on two different test-per-scan BIST architectures to validate its efficiency and reliability. The proposed method demonstrates improved fault coverage, reduced power dissipation, lower hardware complexity, and enhanced overall testing performance compared to conventional scan-based BIST techniques. Experimental simulations and functional verification are carried out using the Xilinx ISE design suite, and the obtained results confirm the effectiveness of the proposed architecture in achieving accurate, reliable, and cost-effective VLSI testing.