Low-Power CAM-Based In-Memory Multiplier with Operand Bypass Optimization

Abstract

This work presents an enhanced in-memory computation (IMC) based multiplier architecture incorporating a power-aware operand activity detection mechanism for further reduction of dynamic power consumption. The conventional IMC multiplier utilizes Content Addressable Memory (CAM), Block RAM (BRAM), and associative processing to perform multiplication through address mapping and memory-based computation, thereby minimizing data movement and eliminating the need for a dedicated arithmetic logic unit. In the proposed extension, an operand activity detector is introduced to identify trivial multiplication conditions such as multiplication by zero and multiplication by one. For these cases, the computation is bypassed and the output is generated directly without activating the CAM search and associative processing stages. This approach significantly reduces unnecessary switching activity, memory access operations, and computational overhead. The architecture is implemented using Verilog HDL and targeted for FPGA realization using Xilinx Vivado. Simulation results demonstrate correct functionality while achieving improved energy efficiency compared to the original IMC multiplier architecture. The proposed design preserves computational accuracy and offers a simple yet effective low-power enhancement suitable for embedded systems, edge devices, and energy-constrained digital signal processing applications.