A DESIGN AND SIMULATION OF LOW POWER 18T HYBRID MASTER-SLAVE FLIP-FLOP USING FREQUENCY DIVIDER

Abstract

Frequency dividers play a crucial role in modern VLSI systems for clock generation, timing control, and communication applications. The performance of these systems highly depends on the efficiency of the flip-flop used. This paper presents the design and simulation of a low-power 18-transistor (18T) hybrid master–slave flip-flop for frequency divider applications. The proposed design combines pass-transistor logic and static CMOS logic with singlephase clocking to achieve reduced power consumption, propagation delay, and silicon area. It incorporates a levelrestoring circuit in the master stage and a transistor stacking technique in the slave stage to minimize leakage power and enhance stability. Implemented using 90 nm CMOS technology, the proposed flipflop demonstrates improved energy efficiency and reliable operation up to 1 GHz. The proposed circuit significantly reduces power dissipation and delay, making it suitable for high-speed and low- power VLSI applications.